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general description the max8550/max8551 integrate a synchronous-buck pwm controller to generate v ddq , a sourcing and sinking ldo linear regulator to generate v tt , and a 10ma refer- ence output buffer to generate v ttr . the buck controller drives two external n-channel mosfets to generate out- put voltages down to 0.7v from a 2v to 28v input with out- put currents up to 15a. the ldo can sink or source up to 1.5a continuous and 3a peak current. both the ldo out- put and the 10ma reference buffer output can be made to track the refin voltage. these features make the max8550/max8551 ideally suited for ddr memory appli- cations in desktops, notebooks, and graphic cards. the pwm controller in the max8550/max8551 utilizes maxim? proprietary quick-pwm architecture with pro- grammable switching frequencies of up to 600khz. this control scheme handles wide input/output voltage ratios with ease and provides 100ns response to load tran- sients while maintaining high efficiency and a relatively constant switching frequency. the max8550 offers fully programmable uvp/ovp and skip-mode options ideal in portable applications. skip mode allows for improved efficiency at lighter loads. the max8551, which is tar- geted towards desktop and graphic-card applications, does not offer the pulse-skip feature. the vtt and vttr outputs track to within 1% of v refin / 2. the high bandwidth of this ldo regulator allows excel- lent transient response without the need for bulk capac- itors, thus reducing cost and size. the buck controller and ldo regulators are provided with independent current limits. adjustable lossless foldback current limit for the buck regulator is achieved by monitor- ing the drain-to-source voltage drop of the low-side mos- fet. additionally, overvoltage and undervoltage protection mechanisms are built in. once the overcurrent condition is removed, the regulator is allowed to enter soft-start again. this helps minimize power dissipation during a short-circuit condition. the max8550/max8551 allow flexible sequencing and standby power manage- ment using the shdna , shdnb , and stby inputs. both the max8550 and max8551 are available in a small 5mm 5mm, 28-pin thin qfn package. applications ddr i and ddr ii memory power supplies desktop computers notebooks and desknotes graphic cards game consoles raid networking features buck controller ? quick-pwm with 100ns load-step response ? up to 95% efficiency ? 2v to 28v input voltage range ? 1.8v/2.5v fixed or 0.7v to 5.5v adjustable output ? up to 600khz selectable switching frequency ? programmable current limit with foldback capability ? 1.7ms digital soft-start and independent shutdown ? overvoltage/undervoltage-protection option ? power-good window comparator ldo section ? fully integrated vtt and vttr capability ? vtt has 3a sourcing/sinking capability ? vtt and vttr outputs track v refin / 2 ? all-ceramic output-capacitor designs ? 1.0v to 2.8v input voltage range ? power-good window comparator max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ________________________________________________________________ maxim integrated products 1 part temp range pin-package max8550 eti -40 c to +85 c 28 5mm 5mm tqfn max8550eti+ -40 c to +85 c 28 5mm 5mm tqfn max8551 eti -40 c to +85 c 28 5mm 5mm tqfn ordering information 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 max8550 max8551 5mm x 5mm thin qfn top view ovp/uvp (n.c. for max8551) ton ref ilim pok1 pok2 stby shdnb shdna av dd skip (tp1 for m ax8551) gnd pgnd1 v dd dl bst lx dh v in out fb refin vtti vtt pgnd2 vttr vtts ss pin configuration 19-3173; rev 2; 9/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit appears at end of data sheet. quick-pwm is a trademark of maxim integrated products, inc. + denotes lead-free package.
parameter symbol conditions min typ max units main pwm controller v in 228 input voltage range v dd , av dd 4.5 5.5 v output adjust range v out 0.7 5.5 v fb = out 0.693 0.7 0.707 fb = gnd 2.47 2.5 2.53 output voltage accuracy (note 2) fb = v dd 1.78 1.8 1.82 v soft-start ramp time t ss rising edge of shdna to full current limit 1.7 ms ton = gnd (600khz) 170 194 219 ton = ref (450khz) 213 243 273 ton = open (300khz) 316 352 389 on-time t on v in = 15v, v out = 1.5v (note 3) ton = av dd (200khz) 461 516 571 ns minimum off-time t off_min (note 3) 200 300 450 ns v in quiescent supply current i in 25 40 ? v in shutdown supply current shdna = shdnb = gnd 1 5 ? all on (pwm, vtt, and vttr on) 2.5 5 shdna = gnd (only vtt and vttr on) 2 4 stby = av dd (only vttr and pwm on) 1 2 av dd quiescent supply current i avdd shdnb = gnd (only pwm on) 0.5 1 ma av dd + v dd shutdown supply current shdna = shdnb = gnd 2 10 a rising edge of v in 4.1 4.25 4.4 v av dd undervoltage-lockout threshold hysteresis 50 mv v dd quiescent supply current i vdd set v fb = 0.8v 1 5 ? max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = +15v, v dd = av dd = v shdna = v shdnb = v bst = v ilim = 5v, v out = v refin = v vtti = 2.5v, uvp/ovp = stby = fb = skip = gnd, pgnd1 = pgnd2 = lx = gnd, ton = open, v vtts = v vtt , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v in to gnd .............................................................-0.3v to +30v v dd, av dd , vtti to gnd .........................................-0.3v to +6v shdna , shdnb , refin to gnd..............................-0.3v to +6v ss, pok1, pok2, skip , ilim, fb to gnd ................-0.3v to +6v stby, ton, ref, uvp/ovp to gnd ........-0.3v to (av dd + 0.3v) out, vttr to gnd ..................................-0.3v to (av dd + 0.3v) dl to pgnd1..............................................-0.3v to (v dd + 0.3v) dh to lx ....................................................-0.3v to (v bst + 0.3v) lx to bst..................................................................-6v to +0.3v lx to gnd .................................................................-2v to +30v vtt to gnd...............................................-0.3v to (v vtti + 0.3v) vtts to gnd............................................-0.3v to (av dd + 0.3v) pgnd1, pgnd2 to gnd .......................................-0.3v to +0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70?) 28-pin 5mm x 5mm tqfn (derate 35.7mw/? above +70?).................................................................2.86w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +165? lead temperature (soldering, 10s) .................................+300?
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units reference reference voltage v ref av dd = 4.5v to 5.5v; i ref = 0 1.98 2 2.02 v reference load regulation i ref = 0 to 50? 0.01 v v ref rising 1.93 v ref undervoltage lockout hysteresis 300 mv fault detection ovp trip threshold (referred to nominal v out ) uvp/ovp = avdd (note 4) 112 116 120 % uvp trip threshold (referred to nominal v out ) 65 70 75 % lower level, falling edge, 1% hysteresis 87 90 93 pok1 trip threshold (referred to nominal v out ) upper level, rising edge, 1% hysteresis 107 110 113 % lower level, falling edge, 1% hysteresis 87.5 90 92.5 pok2 trip threshold (referred to nominal v vtts and v vttr ) upper level, rising edge, 1% hysteresis 107.5 110 112.5 % uvp blanking time from rising edge of shdna 10 20 40 ms ovp, uvp, pok_ propagation delay ovp not applicable in max8551 10 ? pok_ output low voltage i sink = 4ma 0.3 v pok_ leakage current v pok_ = 5.5v, v fb = 0.8v, v vtts = 1.3v 1 a ilim adjustment range v ilim 0.25 2.00 v ilim input leakage current 0.1 ? current-limit threshold (fixed) pgnd1 to lx 45 50 55 mv current-limit threshold (adjustable) pgnd1 to lx v ilim = 2v 170 200 235 mv current-limit threshold (negative direction) pgnd1 to lx skip = av dd (note 4) -75 -60 -45 mv current-limit threshold (negative direction) pgnd1 to lx skip = av dd , v ilim = 2v (note 4) -250 mv zero-crossing detection threshold pgnd1 to lx 3mv thermal-shutdown threshold +160 ? thermal-shutdown hysteresis 15 ? electrical characteristics (continued) (v in = +15v, v dd = av dd = v shdna = v shdnb = v bst = v ilim = 5v, v out = v refin = v vtti = 2.5v, uvp/ovp = stby = fb = skip = gnd, pgnd1 = pgnd2 = lx = gnd, ton = open, v vtts = v vtt , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units mosfet drivers dh gate-driver on-resistance v bst - v lx = 5v 1 4 ? dl gate-driver on-resistance in high state 14 ? dl gate-driver on-resistance in low state 0.5 3 ? dh falling to dl rising 30 dead time (additional to adaptive delay) dl falling to dh rising 30 ns inputs and outputs rising edge 1.20 1.7 2.20 v logic input threshold ( shdn_ , stby, skip (note 4)) hysteresis 225 mv logic input current ( shdn_ , stby, skip (note 4)) -1 +1 ? low (2.5v output) 0.05 dual-mode input logic levels (fb) high (1.8v output) 2.1 v input bias current (fb) -0.1 +0.1 ? high av dd - 0.4 floating 3.15 3.85 ref 1.65 2.35 four-level input logic levels (ton, ovp/uvp (note 4)) low 0.5 v logic input current (ton, ovp/uvp (note 4)) -3 +3 ? fb = gnd 90 175 350 fb = av dd 70 135 270 out input resistance fb adjustable mode 400 800 1600 k ? out discharge-mode on-resistance (note 4) 10 25 ? dl turn-on level during discharge mode (measured at out) (note 4) 0.3 v electrical characteristics (continued) (v in = +15v, v dd = av dd = v shdna = v shdnb = v bst = v ilim = 5v, v out = v refin = v vtti = 2.5v, uvp/ovp = stby = fb = skip = gnd, pgnd1 = pgnd2 = lx = gnd, ton = open, v vtts = v vtt , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) dual mode is a trademark of maxim integrated products, inc.
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards _______________________________________________________________________________________ 5 note 1: specifications to -40? are guaranteed by design, not production tested. note 2: when the inductor is in continuous conduction, the output voltage has a dc regulation level higher than the error-compara- tor threshold by 50% of the ripple. in discontinuous conduction, the output voltage has a dc regulation level higher than the trip level by approximately 1.5% due to slope compensation. note 3: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = gnd, v bst = 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times may differ due to mosfet switching speeds. note 4: not applicable to the max8551. parameter symbol conditions min typ max units linear regulators (vttr and vtt) vtti input voltage range v vtti 1 2.8 v vtti supply current i vtti i vtt = i vttr = 0 <0.1 1ma vtti shutdown current shdna = shdnb = gnd 10 ? refin input impedance v refin = 2.5v 12 20 30 k ? refin range v refin 1 2.8 v v refin rising 0.7 0.9 v refin lockout threshold hysteresis 75 mv soft-start charge current i ss v ss = 0 4 ? vtt internal mosfet high-side on-resistance i vtt = -100ma, v vtti = 1.5v, av dd = 4.5v 0.3 ? vtt internal mosfet low-side on-resistance i vtt = 100ma, av dd = 4.5v 0.3 ? vtt output accuracy (referred to v refin / 2) v refin = 1.5v or 2.5v, i vtt = 1ma -1 +1 % v refin = 2.5v, i vtt = 0 to 1.5a 1 vtt load regulation v refin = 1.5v, i vtt = 0 to 1a 1 % vtt current limit vtt = 0 or vtti ? ? ?.5 a vtts input current i vtts v vtts = 1.5v, vtt open 0.1 1a vttr output error (referred to v refin / 2) v refin = 1.5v or 2.5v, i vttr = 0 -1 +1 % vttr current limit v vttr = 0 or v vtti ?3 ?0 ?0 ma electrical characteristics (continued) (v in = +15v, v dd = av dd = v shdna = v shdnb = v bst = v ilim = 5v, v out = v refin = v vtti = 2.5v, uvp/ovp = stby = fb = skip = gnd, pgnd1 = pgnd2 = lx = gnd, ton = open, v vtts = v vtt , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 6 _______________________________________________________________________________________ typical operating characteristics (v vin = 12v, v out = 2.5v, ton = gnd, skip = av dd , circuit of figure 8, t a = +25?, unless otherwise noted.) efficiency vs. load current (ton = gnd) max8550/51 toc01 i load (a) efficiency (%) 10 1 0.1 60 70 80 90 100 50 10 20 30 40 0 0.01 100 f sw = 600khz v out = 2.5v v out = 1.8v v out = 1.5v skip = gnd skip = av dd efficiency vs. load current (ton = open) max8550/51 toc02 i load (a) efficiency (%) 10 1 0.1 10 20 30 40 50 60 70 80 90 100 0 0.01 100 f sw = 300khz v out = 2.5v v out = 1.8v v out = 1.5v skip = gnd skip = av dd switching frequency vs. load current (ton = gnd) max8550/51 toc03 i load (a) frequency (khz) 11 10 8 9 2 3 4 5 6 7 1 50 100 150 200 250 300 350 400 450 500 550 600 650 700 0 012 skip = gnd skip = av dd switching frequency vs. input voltage (ton = gnd) max8550/51 toc04 v in (v) frequency (khz) 26 24 20 22 8 10 12 14 16 18 6 420 440 460 480 500 540 520 560 580 600 620 640 660 680 700 400 428 i load = 12a i load = 0a switching frequency vs. temperature (ton = gnd) max8550/51 toc05 temperature ( c) frequency (khz) 80 65 50 35 20 5 -10 -25 650 660 670 680 690 700 600 640 630 620 610 -40 i load = 12a output voltage vs. load current max8550/51 toc06 i load (a) v out (v) 12 10 6 8 4 2 2.495 2.500 2.505 2.510 2.515 2.520 2.525 2.530 2.535 2.540 2.490 014 v in = 15v, ton = gnd skip = gnd skip = av dd vtt voltage vs. vtt current max8550/51 toc07 i vtt (a) v vtt (v) 2 1 -2 -1 0 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.20 -3 3 vttr voltage vs. vttr current max8550/51 toc08 i vttr (ma) v vttr (v) 10 5 -10 -5 0 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.20 -15 15 line regulation (v out vs. v in ) max8550/51 toc09 v in (v) v out ( v ) 26 24 20 22 8 10 12 14 16 18 6 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.45 428 i load = 0a i load = 12a
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards _______________________________________________________________________________________ 7 load transient (buck) max8550/51 toc10 20 s/div 12a v out 100mv/div vtt 100mv/div vttr 100mv/div i load 10a/div 0.1a i vtt = 1.5a, i vttr = 15ma load transient vtt (-1.5a to +1.5a) max8550/51 toc11 40 s/div v out 50mv/div vtt 50mv/div vttr 50mv/div i vtt 2a/div 0a i load = 12a, i vttr = 15ma load transient vtt (-3a to +3a) max8550/51 toc12 40 s/div v out 50mv/div vtt 50mv/div vttr 50mv/div i vtt 5a/div 0a i load = 12a, i vttr = 15ma power-up waveforms max8550/51 toc13 200 s/div out 1v/div vtt 2v/div vttr 1v/div v in 10v/div 0v 0v 0v 0v v dd = 5v, i load = 12a, i vtt = 1.5a, i vttr = 15ma power-down waveforms max8550/51 toc14 200 s/div out 1v/div vtt 2v/div vttr 1v/div v in 10v/div 0v 0v 0v 0v v dd = 5v, i load = 12a, i vtt = 1.5a, i vttr = 15ma v ddq startup and shutdown into heavy load, discharge disabled max8550/51 toc15 1ms/div v out 2v/div vtt 1v/div shdna + shdnb 5v/div pok1 5v/div 0v 0v 0v 0v i load = 12a, i vtt = 1.5a typical operating characteristics (continued) (v vin = 12v, v out = 2.5v, ton = gnd, skip = av dd , circuit of figure 8, t a = +25?, unless otherwise noted.) v ddq startup and shutdown into light load, discharge enabled max8550/51 toc16 2ms/div v out 1v/div vtt 1v/div shdna + shdnb 5v/div pok1 5v/div 0v 0v 0v 0v r load = 10 ? , r vtt = 20 ? vtt, vttr startup and shutdown max8550/51 toc17 200 s/div vtt 1v/div vttr 1v/div shdnb 5v/div pok2 5v/div 0v 0v 0v 0v i vtt = 1.5a, i vttr = 15ma
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 8 _______________________________________________________________________________________ overvoltage and turn-off of buck output max8550/51 toc18 20 s/div v out 2v/div i l 25a/div dl 5v/div dh 20v/div 0v 0v 0v 0a typical operating characteristics (continued) (v vin = 12v, v out = 2.5v, ton = gnd, skip = av dd , circuit of figure 8, t a = +25?, unless otherwise noted.) short circuit and recovery of v ddq max8550/51 toc19 400 s/div v out 2v/div i load 10a/div v in 10v/div i in 2a/div 0a 0v 0a 0v uvp disabled, foldback current limit short circuit and recovery of v ddq max8550/51 toc20 400 s/div v out 2v/div i load 10a/div v in 10v/div i in 2a/div 0a 0v 0a 0v uvp enabled short circuit of vtt max8550/51 toc21 400 s/div vtt 1v/div i vtt 5a/div 0a 0v
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards _______________________________________________________________________________________ 9 pin description pin name function 1ton on-time selection-control input. this four-level logic input sets the nominal dh on-time. connect to gnd, ref, av dd , or leave ton unconnected to select the following nominal switching frequencies: ton = av dd (200khz) ton = open (300khz) ton = ref (450khz) ton = gnd (600khz) ovp/ uvp (max8550) overvoltage/undervoltage-protection control input. this four-level logic input enables or disables the overvoltage and/or undervoltage protection. the overvoltage limit is 116% of the nominal output voltage. the undervoltage limit is 70% of the nominal output voltage. discharge mode is enabled when ovp is also enabled. connect the ovp/uvp pin to the following pins for the desired function: ovp/uvp = av dd (enable ovp and discharge mode, enable uvp.) ovp/uvp = open (enable ovp and discharge mode, disable uvp.) ovp/uvp = ref (disable ovp and discharge mode, enable uvp.) ovp/uvp = gnd (disable ovp and discharge mode, disable uvp.) 2 n.c. (max8551) do not connect; leave open.* 3 ref +2.0v reference voltage output. bypass to gnd with a 0.1? (min) capacitor. ref can supply 50? for external loads. can be used for setting voltage for ilim. ref turns off when shdna , shdnb , and stby are low. 4 ilim valley current-limit threshold adjustment for buck regulator. the current-limit threshold across pgnd and lx is 0.1 times the voltage at ilim. connect ilim to a resistive divider, typically from ref to gnd, to set the current-limit threshold between 25mv and 200mv. this corresponds to a 0.25v to 2v range at ilim. connect ilim to av dd to select the 50mv default current-limit threshold. see the setting the current limit section. 5 pok1 buck power-good open-drain output. pok1 is low when the buck output voltage is more than 10% above or below the normal regulation point or during soft-start. pok1 is high impedance when the output is in regulation and the soft-start circuit has terminated. pok1 is low in shutdown. 6 pok2 ldo power-good open-drain output. in normal mode, pok2 is low when either vttr or vtts is more than 10% above or below the normal regulation point, which is typically refin / 2. in standby mode, pok2 responds only to the vttr input. pok2 is low in shutdown, and when v refin is less than 0.8v. 7 stby standby. connect to high for low-quiescent mode where the vtt output is disabled, but the vttr buffer is kept alive if shdnb is high. pok2 takes input from only vttr in this mode. pwm output can be on or off, depending on the state of shdna . 8ss soft-start control for vtt and vttr. connect a capacitor (c9 in the typical applications circuit ) from ss to ground (see the soft-start capacitor selection section). leave ss open to disable soft-start. ss discharges to ground when shdnb is low. see the por, uvlo, and soft-start section. 9 vtts sensing pin for termination supply output. normally connected to vtt pin to allow accurate regulation to half the refin voltage. connected to a resistive divider from vtt to gnd to regulate vtt to higher than half the refin voltage. 10 vttr termination reference voltage. vttr tracks v refin / 2. * the max8551 has no ovp or discharge-mode feature. only uvp is available.
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 10 ______________________________________________________________________________________ pin description (continued) pin name function 11 pgnd2 power ground for vtt and vttr. connect pgnd2 externally to the underside of the exposed pad. 12 vtt termination power-supply output. connect vtt to vtts to regulate to v refin / 2. 13 vtti power-supply input voltage for vtt and vttr. normally connected to the output of the buck regulator for ddr application. 14 refin external reference input. this is used to regulate the vtt and vttr outputs to v refin / 2. 15 fb feedback input for buck output. connect to av dd for a +1.8v fixed output or to gnd for a +2.5v fixed output. for an adjustable output (0.7v to 5.5v), connect fb to a resistive divider from the output voltage. fb regulates to +0.7v. 16 out output-voltage sense connection. connect to the positive terminal of the buck output filter capacitor. out senses the output voltage to determine the on-time for the high-side switching mosfet (q1 in the typical applications circuit ). out also serves as the buck output? feedback input in fixed-output modes. when discharge mode is enabled by ovp/uvp, the output capacitor is discharged through an internal 10 ? resistor connected between out and gnd. 17 v in input-voltage sense connection. connect to input power source. v in is used only to set the pwm? on- time one-shot timer. in voltage range is from 2v to 28v. 18 dh high-side gate-driver output. swings from lx to bst. dh is low when in shutdown or uvlo. 19 lx external inductor connection. connect lx to the input side of the inductor. lx is used for both current limit and the return supply of the dh driver. 20 bst boost flying-capacitor connection. connect to an external capacitor and diode according to the typical applications circuit (figure 8). see the boost-supply diode and capacitor selection section. 21 dl synchronous-rectifier gate-driver output. swings from pgnd to v dd . 22 v dd supply input for the dl gate drive. connect to the +4.5v to +5.5v system supply voltage. bypass to pgnd1 with a 1? (min) ceramic capacitor. 23 pgnd1 power ground for buck controller. connect pgnd1 externally to the underside of the exposed pad. 24 gnd analog ground for both buck and ldo. connect gnd externally to the underside of the exposed pad. skip (max8550) pulse-skipping control input. connect to av dd for low-noise, forced-pwm mode. connect to gnd to enable pulse-skipping operation. 25 tp1 (max8551) in the max8551, this pin is a test pin and must be connected to gnd (pin 24). 26 av dd analog supply input for both buck and ldo. connect to the +4.5v to +5.5v system supply voltage with a series 10 ? resistor. bypass to gnd with a 1? or greater ceramic capacitor. 27 shdna shutdown control input a. use to control buck output. a rising edge on shdna clears the overvoltage and undervoltage-protection fault latches (see tables 2 and 3). connect to av dd for normal operation. 28 shdnb shutdown control input b. use to control vtt and vttr outputs. both vttr and vtt are high impedence in shutdown (see table 2).
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 11 max8550/ max8551 s r q s r q on-time compute t on one-shot 1.0v lx lx 1.16 x intref ovp/uvp latch quad level decode 20ms timer 0.7 x intref intref fb decode discharge logic n 2v reference intref v out = 1.8v v out = 2.5v n intref + 10% intref - 10% n power-down* *power-down forces pok2 low and vtt, vttr to high impedance. +0.4v 10k ? 10k ? refin / 2 refin / 2 - 10% refin / 2 + 10% refin / 2 - 10% refin / 2 + 10% in bst dh lx v dd dl pgnd ilim v dd - 1v out av dd gnd ref refin vtt v dd v dd n n pgnd2 vttr ss pok2 fb pok1 ovp/uvp (n.c. in max8551) ton t off q trig one-shot q trig zero crossing vtts vtti current limits vtt ilim vttr ilim stby shutdown decoder buck on/off vtt on/off vttr on/off bias on/off shdna shdnb skip (tp1 in max8551 must be connected to gnd) vtti pgnd2 out figure 1. functional diagram
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 12 ______________________________________________________________________________________ detailed description the max8550/max8551 combine a synchronous-buck pwm controller, an ldo linear regulator, and a 10ma ref- erence output buffer. the buck controller drives two exter- nal n-channel mosfets to deliver load currents up to 12a and generate voltages down to 0.7v from a +2v to +28v input. the ldo linear regulator can sink and source up to 1.5a continuous and 3a peak current with relatively fast response. these features make the max8550/ max8551 ideally suited for ddr memory applications. the max8550/max8551 buck regulator is equipped with a fixed switching frequency of up to 600khz using maxim? proprietary constant on-time quick-pwm architecture. this control scheme handles wide input/output voltage ratios with ease, and provides 100ns ?nstant-on?response to load transients, while maintaining high efficiency with relatively constant switching frequency. the buck controller, ldo, and a reference output buffer are provided with independent current limits. lossless foldback current limit in the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low-side fet. the ilim input is used to adjust this current limit. overvoltage protection, if selected, is achieved by latching the low-side synchro- nous fet on and the high-side fet off when the output voltage is over 116% of its set output. it also features an optional undervoltage protection by latching the mosfet drivers to the off state during an overcurrent condition, when the output voltage is lower than 70% of the regulated output. this helps minimize power dissi- pation during a short-circuit condition. the current limit in the ldo and buffered reference out- put buffer is ?a and ?0ma, respectively, and neither have the over- or undervoltage protection. when the current limit in either output is reached, the output no longer regulates the voltage, but regulates the current to the value of the current limit. +5v bias supply (v dd and av dd ) the max8550/max8551 require an external +5v bias supply in addition to the input voltage (v in ). keeping the bias supply external to the ic improves the efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and the gate drivers. if stand-alone capabili- ty is needed, then the +5v supply can be generated with an external linear regulator such as the max1615. v dd , av dd , and in can be connected together if the input source is a fixed +4.5v to +5.5v supply. v dd is the supply input for the buck regulator? mosfet drivers, and av dd supplies the power for the rest of the ic. the current from the av dd and v dd power supply must supply the current for the ic and the gate drive for the mosfets. this maximum current can be estimated as: where i vdd + i avdd are the quiescent supply currents into v dd and av dd , q g1 and q g2 are the total gate charges of mosfets q1 and q2 (at v gs = 5v) in the typical applications circuit , and f sw is the switching frequency. free-running constant-on-time pwm the quick-pwm control architecture is a pseudo-fixed- frequency, constant on-time, current-mode regulator with voltage feed-forward (figure 1). this architecture relies on the output filter capacitor? esr to act as a current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely pro- portional to input voltage and directly proportional to the output voltage. another one-shot sets a minimum off-time of 300ns (typ). the on-time one-shot is trig- gered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to input and output voltages. the high-side switch on-time is inversely proportional to the input volt- age (v in ) and is proportional to the output voltage: where k (the switching period) is set by the ton input connection (table 1) and r ds(on)q2 is the on-resis- tance of the synchronous rectifier (q2) in the typical applications circuit (figure 8). this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensi- tive regions such as the 455khz if band. tk vi r v on out load ds on q in () = + () 2 iiifqq bias vdd avdd sw gg =+ ++ () 12
2) the inductor ripple-current operating point remains relatively constant, resulting in an easy design methodology and predictable output voltage ripple. the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics table (approximately ?2.5% at 600khz and 450khz, and ?0% at 200khz and 300khz). on-times at operat- ing points far removed from the conditions specified in the electrical characteristics table can vary over a wider range. for example, the 600khz setting typically runs approximately 10% slower with inputs much greater than 5v due to the very short on-times required. the constant on-time translates only roughly to a con- stant switching frequency. the on-times guaranteed in the electrical characteristics table are influenced by resistive losses and by switching delays in the high- side mosfet. resistive losses, which include the inductor, both mosfets, the output capacitor? esr, and any pc board copper losses in the output and ground, tend to raise the switching frequency as the load increases. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective on- time. the dead time occurs only in pwm mode ( skip = v dd ) and during dynamic output-voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the induc- tor? emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchro- nous rectifier, the inductor, and any pc board resis- tances; v drop2 is the sum of the resistances in the charging path, including the high-side switch (q1 in the typical applications circuit ), the inductor, and any pc board resistances, and t on is the one-shot on-time (see the on-time one-shot (ton) section. automatic pulse-skipping mode ( skip = gnd) in skip mode ( skip = gnd), an inherent automatic switchover to pfm takes place at light loads (figure 2). this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor cur- rent? zero crossing. the zero-crossing comparator differentially senses the inductor current across the synchronous-rectifier mosfet (q2 in the typical applications circuit , figure 8). once v pgnd - v lx drops below 5% of the current-limit threshold (2.5mv for the default 50mv current-limit threshold), the com- parator forces dl low (figure 1). this mechanism caus- es the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to half the peak-to-peak ripple current, which is a function of the inductor value (figure 2). this threshold is rela- tively constant, with only a minor dependence on the input voltage (v in ): where k is the on-time scale factor (see table 1). for example, in the typical applications circuit of figure 8 (k = 1.7?, v out = 2.5v, v in = 12v, and l = 1?), the pulse-skipping switchover occurs at: the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switch- ing waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. 25 17 21 12 2 12 168 . . . vs h v v a ? ? ? ? ? ? ? ? ? ? ? ? = - .5v i vk l vv v load skip out in out in () = ? ? ? ? ? ? ? ? ? ? ? ? 2 - f vv tv v sw out drop on in drop = + + () 1 2 max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 13 table 1. approximate k-factor errors ton setting typical k- factor (s) k-factor error (%) minimum v in at v out = 2.5v (h = 1.5, see the dropout performance section) 200 (ton = av dd ) 5.0 10 3.15 300 (ton = open) 3.3 10 3.47 450 (ton = ref) 2.2 12.5 4.13 600 (ton = gnd) 1.7 12.5 5.61
max8550/max8551 light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broad- er efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resis- tance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. dc output accuracy specifications refer to the thresh- old of the error comparator. when the inductor is in continuous conduction, the max8550/max8551 regu- late the valley of the output ripple, so the actual dc out- put voltage is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction ( skip = gnd and i load < i load( skip ) ), the output volt- age has a dc regulation level higher than the error- comparator threshold by approximately 1.5% due to slope compensation. forced-pwm mode ( skip = av dd in max8550 only) the low-noise forced-pwm mode ( skip = av dd ) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factor of v out / v in . forced-pwm mode keeps the switching frequency fairly constant. however, forced-pwm opera- tion comes at a cost where the no-load v dd bias cur- rent remains between 2ma and 20ma due to the external mosfet? gate charge and switching frequen- cy. forced-pwm mode is most useful for reducing audio frequency noise, improving load-transient response, and providing sink-current capability for dynamic output-voltage adjustment. current-limit buck regulator (ilim) valley current limit the current-limit circuit for the buck regulator portion of the max8550/max8551 employs a unique ?alley?cur- rent-sensing algorithm that senses the voltage drop across lx and pgnd1 and uses the on-resistance of the rectifying mosfet (q2 in the typical applications circuit , figure 8) as the current-sensing element. if the magnitude of the current-sense signal is above the val- ley current-limit threshold, the pwm controller is not allowed to initiate a new cycle (figure 4). with valley current-limit sensing, the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor current ripple. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and input voltage. when combined with the undervoltage-protection circuit, this current-limit method is effective in almost every circumstance. in forced-pwm mode, the max8550/max8551 also implement a negative current limit to prevent excessive reverse inductor currents when the buck regulator output is sinking current. the negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when v ilim is adjust- ed. the current-limit threshold is adjusted with an exter- nal resistor-divider at ilim. a 2? to 20? divider current is recommended for accuracy and noise immunity. the current-limit threshold adjustment range is from 25mv to 200mv. in the adjustable mode, the current- limit threshold voltage (from pgnd1 to lx) is precisely 1/10th the voltage seen at ilim. the threshold defaults to 50mv when ilim is connected to av dd . the logic threshold for switchover to the 50mv default value is approximately av dd - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the differ- ential current-sense signals seen between lx and gnd. integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 14 ______________________________________________________________________________________ figure 2. pulse-skipping/discontinuous crossover point inductor current on-time 0 time i peak i load = i peak / 2 ? i ? t v in - v out l =
por, uvlo, and soft-start internal power-on reset (por) occurs when av dd rises above approximately 2v, resetting the fault latch and the soft-start counter, powering up the reference, and preparing the buck regulator for operation. until av dd reaches 4.25v (typ), av dd undervoltage-lockout (uvlo) circuitry inhibits switching. the controller inhibits switching by pulling dh low and holding dl low when ovp and shutdown discharge are disabled (ovp/uvp = ref or gnd) or forcing dl high when ovp and shutdown discharge are enabled (ovp/uvp = av dd or open). see table 3 for a detailed truth table for ovp/uvp and shutdown settings. when av dd rises above 4.25v, the controller activates the buck regulator and initializes the internal soft-start. the buck regulator? internal soft-start allows a gradual increase of the current-limit level during startup to reduce the input surge currents. the max8550/ max8551 divide the soft-start period into five phases. during the first phase, the controller limits the current limit to only 20% of the full current limit. if the output does not reach regulation within 425?, soft-start enters the second phase, and the current limit is increased by another 20%. this process repeats until the maximum current limit is reached, after 1.7ms, or when the output reaches the nominal regulation voltage, whichever occurs first. adding a capacitor in parallel with the external ilim resistors creates a continuously adjustable analog soft-start function for the buck regu- lator? output. soft-start in the ldo section can be realized by con- necting a capacitor between the ss pin and ground. when shdnb is driven low, or during thermal shut- down of the ldos, the ss capacitor is discharged. when shdnb is driven high or when the thermal limit is removed, an internal 4? (typ) current charges the ss capacitor. the resulting ramp voltage on ss linearly increases the current-limit comparator thresholds to both the vtt and vttr outputs, until full current limit is max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 15 figure 4. valley current-limit threshold inductor current i load i limit 0 time i peak i load(max) i lim(val) = 1 - x i load lir 2 () figure 3. adjustable current-limit threshold ilim to pwm controller (see figure 1) v dd - 1v max8550/ max8551 lx 1.0v c ref c ilim r a r b ref
max8550/max8551 attained when ss reaches approximately 1.6v. this lowering of the current limit during startup limits the ini- tial inrush current peaks, particularly when driving capacitors. choose the value of the ss cap appropri- ately to set the soft-start time window. leave ss floating to disable the soft-start feature. power-ok (pok1) pok1 is an open-drain output for a window comparator that continuously monitors v out . pok1 is actively held low when shdna is low and during the buck regulator output? soft-start. after the digital soft-start terminates, pok1 becomes high impedance as long as the output voltage is within ?0% of the nominal regulation voltage set by fb. when v out drops 10% below or rises 10% above the nominal regulation voltage, the max8550/ max8551 pull pok1 low. any fault condition forces pok1 low until the fault latch is cleared by toggling shdna or cycling av dd power below 1v. for logic-level output voltages, connect an external pullup resistor between pok1 and av dd . a 100k ? resistor works well in most applications. note that the pok1 window detec- tor is completely independent of the overvoltage and undervoltage-protection fault detectors and the state of vtts and vttr. shdna and output discharge the shdna input corresponds to the buck regulator and places the buck regulator? portion of the ic in a low-power mode (see the electrical characteristics table). shdna is also used to reset a fault signal such as an overvoltage or undervoltage fault. when output discharge is enabled, (ovp/uvp = av dd or open) and shdna and shdnb are pulled low, or if uvp is enabled (ovp/uvp = av dd ) and v out falls to 70% of its regulation set point, the max8550 dis- charges the buck regulator output (through the out input) through an internal 10 ? switch to ground. while the output is discharging, dl is forced low and the pwm controller is disabled but the reference remains active to provide an accurate threshold. once the out- put voltage drops below 0.3v, the max8550 shuts down the reference and pulls dl high, effectively clamping the buck output and lx to ground. when output discharge is disabled (ovp/uvp = ref or gnd), the controller does not actively discharge the buck output and the dl driver remains low. under these conditions, the buck output discharge rate is determined by the load current and its output capacitance. the buck regulator detects and latches the discharge-mode state set by the ovp/uvp setting on startup. for the max8551, the ovp/uvp is internally connected to ref, which permanently enables the output dis- charge feature (see table 1). shdnb and stby the shdnb input corresponds to the vtt and vttr outputs, and when driven low, places the linear-regula- tor portion of the ic in a low-power mode (see the electrical characteristics table). when shdnb is pulled low, vtt and vttr are high impedance. the stby input is an active-high input that is used to shut down only the vtt output. when stby is high, vtt is high impedance. the stby input overrides the shdnb input, so even with shdnb high, if stby is high, then the vtt output is inactive. power-ok (pok2) pok2 is the open-drain output for a window compara- tor that continuously monitors the vtts input and vttr output. pok2 is pulled low when refin is less than 0.8v, or when shdnb is pulled low. pok2 is high impedance as long as the output voltage is within ?0% of the nominal regulation voltage as set by refin. when v vtts or v vttr rises 10% above or 10% below its nominal regulation voltage, the max8550/ max8551 pull pok2 low. for logic-level output volt- ages, connect an external pullup resistor between pok2 and av dd . a 100k ? resistor works well in most applications. integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 16 ______________________________________________________________________________________ table 2. shutdown and standby control logic stby shdna shdnb buck output vtt vttr gnd av dd av dd on on on gnd av dd gnd on off off av dd av dd av dd on off on gnd gnd av dd off on on gnd gnd gnd off off off
current limit (ldo for vtt and vttr buffer) the vtt output is a linear regulator that regulates the input (vtti) to half the v refin voltage. the feedback point for vtt is at the vtts input (figure 1). vtt is capable of sinking and sourcing at least 1.5a of continu- ous current and 3a peak current. the current limit for vtt and vttr is typically ?a and ?0ma, respective- ly. when the current limit for either output is reached, the outputs regulate the current, not the voltage. fault protection the max8550/max8551 provide overvoltage/undervolt- age fault protection in the buck controller. select ovp/uvp to enable and disable fault protection as shown in table 3. once activated, the controller contin- uously monitors the output for undervoltage and over- voltage fault conditions. overvoltage protection (ovp) when the output voltage rises above 116% of the nomi- nal regulation voltage (max8550 only) and ovp is enabled (ovp/uvp = av dd or open), the ovp circuit sets the fault latch, shuts down the pwm controller, and immediately pulls dh low and forces dl high. this turns on the synchronous-rectifier mosfet (q2 in the typical applications circuit of figure 8) with a 100% duty cycle, rapidly discharging the output capacitor and clamping the output to ground. note that immedi- ately latching dl high can cause the output voltage to go slightly negative due to energy stored in the output lc circuit at the instant the ovp occurs. if the load can- not tolerate a negative voltage, place a power schottky diode across the output to act as a reverse-polarity clamp. toggle shdna or cycle av dd below 1v to clear the fault latch and restart the controller. ovp is dis- abled when ovp/uvp is connected to ref or gnd (see table 3). ovp only applies to the buck output. the vtt and vttr outputs do not have overvoltage protection. undervoltage protection (uvp) when the output voltage drops below 70% of its regula- tion voltage while uvp is enabled, the controller sets the fault latch and begins the discharge mode (see the shutdown and output discharge section). when the output voltage drops to 0.3v, the synchronous rectifier (q2 in the typical applications circuit ) turns on and clamps the buck output to gnd. uvp is ignored for at least 10ms (min) after startup or after a rising edge on shdna . toggle shdna or cycle av dd power below 1v to clear the fault latch and restart the controller. uvp is disabled when ovp/uvp is left open or connected to gnd (see table 3). uvp only applies to the buck out- put. the vtt and vttr outputs do not have undervolt- age protection. thermal fault protection the max8550/max8551 feature two thermal-fault-pro- tection circuits. one monitors the buck-regulator por- tion of the ic and the other monitors the linear regulator (vtt) and the reference buffer output (vttr). when the junction temperature of the buck-regulator portion of the max8550/max8551 rises above +160?, a thermal sensor activates the fault latch, pulls pok1 low, and shuts down the buck-controller output using discharge mode regardless of the ovp/uvp setting. toggle shdna or cycle av dd below 1v to reactivate the con- troller after the junction temperature cools by 15?. if the vtt and vttr regulator portion of the ic has its die temperature rise above +160 c, then vtt and vttr max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 17 table 3. ovp/uvp fault protection ovp/uvp discharge uvp protection ovp protection av dd yes. dl forced high when shdna and shdnb are low. enabled. discharge sequence activated. dl forced high when shut down. enabled. dh pulled low and dl forced high. open yes. dl forced high when shdna and shdnb are low. disabled. enabled. dh pulled low and dl forced high. ref no. dl forced low when shdna is low. enabled. discharge sequence activated. dl forced high when shut down. disabled. gnd no. dl forced low when shdna is low. disabled. disabled.
max8550/max8551 shut off, go high impedance, and restart after the die portion of the ic cools by 15 c. both thermal faults are independent. for example, if the vtt output is over- loaded to the point that it triggers its thermal fault, the buck regulator continues to function. design procedure firmly establish the input voltage range (v in ) and maxi- mum load current (i load ) in the buck regulator before choosing a switching frequency and inductor operating point (ripple current ratio or lir). the primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four fac- tors dictate the rest of the design: input voltage range. the maximum value (v in(max) ) must accommodate the worst-case voltage. the mini- mum value (v in(min) ) must account for the lowest voltage after drops due to connectors and fuses. if there is a choice, lower input voltages result in better efficiency. maximum load current. there are two values to con- sider. the peak load current (i peak ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing components. switching frequency. this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses proportion- al to frequency and v in 2 . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. inductor operating point. this choice provides trade- offs: size vs. efficiency and transient response vs. out- put ripple. low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip = low at light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. setting the output voltage (buck) preset output voltages the max8550/max8551s?dual-mode operation allows the selection of common voltages without requiring external components (figure 5). connect fb to gnd for a fixed 2.5v output, to av dd for a fixed 1.8v output, or connect fb directly to out for a fixed 0.7v output. setting the buck regulator output (v out ) with a resistive voltage-divider at fb the buck-regulator output voltage can be adjusted from 0.7v to 5.5v using a resistive voltage-divider (figure 6). the max8550/max8551 regulate fb to a fixed refer- ence voltage (0.7v). the adjusted output voltage is: where v fb is 0.7v, r c and r d are shown in figure 6, and v ripple is: setting the vtt and vttr voltages (ldo) the termination power-supply output (vtt) can be set by two different methods. first, the vtt output can be con- nected directly to the vtts input to force vtt to regulate to v refin / 2. secondly, vtt can be forced to regulate higher than v refin / 2 by connecting a resistive v lir i r ripple load max esr = () vv r r v out fb c d ripple =+ ? ? ? ? ? ? + 1 2 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 18 ______________________________________________________________________________________ figure 5. dual-mode feedback decoder max8550/ max8551 fb 0.1v 2.5v (fixed) 1.8v (fixed) to error amplifier ref (2.0v) out
divider from vtt to vtts. the maximum value for vtt is v vtti - v dropout where v dropout = i vtt 0.3 ? (max) at t a = +85?. the termination reference voltage (vttr) tracks 1/2 v refin . inductor selection (buck) the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 12a, v in = 12v, v out = 2.5v, f sw = 600khz, 30% ripple current or lir = 0.3: find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at frequencies up to 200khz. the core must be large enough not to satu- rate at the peak inductor current (i peak ): most inductor manufacturers provide inductors in stan- dard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. input capacitor selection (buck) the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents: i rms has a maximum value of i load / 2 when v in = 2 v out . for most applications, nontantalum capacitors (ceramic, aluminum, pos, or oscon) are preferred due to their resistance to power-up surge currents typi- cal of systems with a mechanical switch or connector in series with the input. if the max8550/max8551 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. in either configuration, choose a capacitor that has less than 10? temperature rise at the rms input current for optimal reliability and lifetime. output capacitor selection (buck) the output filter capacitor must have low enough equiv- alent series resistance (r esr ) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. for processor core voltage converters and other appli- cations in which the output is subject to violent load transients, the output capacitor? size depends on how much r esr is needed to prevent the output from dip- ping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitor? size often depends on how much r esr is needed to maintain an acceptable level of out- put voltage ripple. the output ripple voltage of a step- down controller is approximately equal to the total inductor ripple current multiplied by the output capaci- tor? r esr . therefore, the maximum r esr required to meet ripple specifications is: r v i lir esr ripple load max () r v i esr step load max () ? ii vvv v rms load out in out in = () - ii lir peak load max () =+ ? ? ? ? ? ? 1 2 l vv v khz a h . ( . = 25 12 12 600 12 0 3 1 - 2.5v) l vvv v f i lir out in out in sw load max () = () - max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 19 figure 6. setting v out with a resistive voltage-divider max8550/ max8551 dl pgnd1 gnd lx l fb r d r c c out out q2 v out
max8550/max8551 the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, oscons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high-esr zeros that can affect the overall stability (see the stability requirements section). stability requirements for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: if c out consists of multiple same-value capacitors, as in the typical applications circuit of figure 8, the f esr remains the same as that of a single capacitor. for a typical 600khz application, the esr zero frequen- cy must be well below 190khz, preferably below 100khz. two 150?/4v sanyo pos capacitors are used to provide 12m ? (max) of r esr . this results in a zero at 42khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feed- back loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immediately after the 400ns minimum off- time period has expired. double pulsing is more annoying than harmful, result- ing in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stabil- ity is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. vtt output capacitor selection (ldo) a minimum value of 60? is needed to stabilize the vtt output for load currents up to ?.5a. this value of capaci- tance limits the regulator? unity-gain bandwidth frequen- cy to about 700khz (typ) to allow adequate phase margin for stability. to keep the capacitor acting as a capacitor within the regulator? bandwidth, it is important that ceramic caps with low esr and esl be used. since the gain bandwidth is also determined by the transconductance of the output fets, which increases with load current, the output capacitor needs to be greater than 60f if the load current exceeds 1.5a, but can be smaller than 60f if the maximum load current is less than 1.5a. as a rule, choose the minimum capacitance and maximum esr for the output capaci- tor using the following: resr value is measured at the unity-gain-bandwidth frequency given by approximately: once these conditions for stability are met, additional capacitors including those of electrolytic and tantalum types can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or volt- age ripple at the output. . f c i a gbw out load = 40 15 . . _ _ cf i a rm a i out min load esr max load = = 60 15 5 15 ? : f f where f rc esr sw esr esr out = 1 2 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 20 ______________________________________________________________________________________
vttr output capacitor selection (ldo) the vttr buffer is a scaled-down version of the vtt regulator, with much smaller output transconductance. its compensation cap can therefore be smaller, and its esr larger, than what is required for its larger counter- part. for typical applications requiring load current up to ?0ma, a ceramic cap with a minimum value of 1f is recommended (r esr < 0.3 ? ). connect this cap between vttr and the analog ground plane. vtti input capacitor selection (ldo) both the vtt and vttr output stages are powered from the same vtti input. their output voltages are ref- erenced to the same refin input. the value of the vtti bypass capacitor is chosen to limit the amount of rip- ple/noise at vtti, or the amount of voltage dip during a load transient. typically vtti is connected to the output of the buck regulator, which already has a large bulk capacitor. nevertheless, a ceramic capacitor of at least 10? must be used and must be added and placed as close as possible to the vtti pin. this value must be increased with larger load current, or if the trace from the vtti pin to the power source is long and has signifi- cant impedance. furthermore, to prevent undesirable vtti bounce from coupling back to the refin input and possibly causing instability in the loop, the refin pin should ideally tap its signal from a separate low- impedance dc source rather than directly from the vtti input. if the latter is unavoidable, increase the amount of bypass capacitance at the vtti input and add additional bypass at the refin pin. mosfet selection (buck) the max8550/max8551 drive external, logic-level, n- channel mosfets as the circuit-switch elements. the key selection parameters: on-resistance (r ds(on) ): the lower, the better. maximum drain-to-source voltage (v dss ): should be at least 20% higher than input supply rail at the high- side mosfet? drain. gate charges (q g , q gd , q gs ): the lower the better. choose mosfets with rated r ds(on) at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet that has a conduction loss equal to its switching loss at nominal input voltage and maximum output current (see below). for the low- side mosfet, make sure that it does not spuriously turn on because of dv/dt caused by the high-side mosfet turning on, as this results in shoot-through current degrading efficiency. mosfets with a lower q gd to q gs ratio have higher immunity to dv/dt. for proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage. for the low-side mosfet, the worst case is at v in(max) . for the high-side mosfet, the worst case could be at either v in(min) or v in(max) . the high-side mosfet and low-side mosfet have dif- ferent loss components due to the circuit operation. the low-side mosfet operates as a zero-voltage switch; therefore, major losses are: the channel-conduction loss (p lscc ) the body-diode conduction loss (p lsdc ) the gate-drive loss (p lsdr ): use r ds(on) at t j(max) : where v f is the body-diode forward-voltage drop, t dt is the dead time ( 30ns), and f sw is the switching fre- quency. because of the zero-voltage switch operation, the low-side mosfet gate-drive loss occurs as a result of charging and discharging the input capacitance, (c iss ). this loss is distributed among the average dl gate-driver? pullup and pulldown resistance, r dl ( 1 ? ), and the internal gate resistance (r gate ) of the mosfet ( 2 ? ). the drive power dissipated is given by: the high-side mosfet operates as a duty-cycle control switch and has the following major losses: the channel-conduction loss (p hscc ) the vi overlapping switching loss (p hssw ) the drive loss (p hsdr ) (the high-side mosfet does not have body-diode conduction loss because the diode never conducts current): use r ds(on) at t j(max) : () p v v ir hscc out in load ds on = 2 pcvf r rr lsdr iss gs sw gate gate dl = + 2 pivtf lsdc load f dt sw = 2 () p v v ir lscc out in load ds on = ? ? ? ? ? ? 1 2 - max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 21
max8550/max8551 where i gate is the average dh-driver output current determined by: where r dh is the high-side mosfet driver? on-resis- tance (1 ? typ) and r gate is the internal gate resis- tance of the mosfet ( 2 ? ): where v gs = v dd = 5v. in addition to the losses above, allow about 20% more for additional losses because of mosfet output capacitances and low-side mosfet body-diode reverse-recovery charge dissipated in the high-side mosfet that is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal-resistance specifications to calculate the pc board area needed to maintain the desired maximum operating junction temperature with the above-calculat- ed power dissipations. to reduce emi caused by switching noise, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source, or add resistors in series with dh and dl to slow down the switching transitions. adding series resistors increases the power dissipation of the mosfet, so ensure that this does not overheat the mosfet. mosfet snubber circuit (buck) fast switching transitions cause ringing because of a resonating circuit formed by the parasitic inductance and capacitance at the switching nodes. this high-fre- quency ringing occurs at lx? rising and falling transi- tions and can interfere with circuit performance and generate emi. to dampen this ringing, an optional series rc snubber circuit is added across each switch. below is a simple procedure for selecting the value of the series rc of the snubber circuit: 1) connect a scope probe to measure v lx to pgnd1, and observe the ringing frequency, f r . 2) estimate the circuit parasitic capacitance (c par ) at lx by first finding a capacitor value, which, when connected from lx to pgnd1, reduces the ringing frequency by half. c par can then be calculated as 1/3rd the value of the capacitor value found. 3) estimate the circuit parasitic capacitance (l par ) from the equation: 4) calculate the resistor for critical dampening (r snub ) from the equation: r snub = 2 f r x l par . adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. 5) the capacitor (c snub ) should be at least 2 to 4 times the value of c par to be effective. the power loss of the snubber circuit (p rsnub ) is dissi- pated in the resistor and can be calculated as: where v in is the input voltage and f sw is the switching frequency. choose an r snub power rating that meets the specific application? derating rule for the power dissipation calculated. setting the current limit (buck) the current-sense method used in the max8550/ max8551 makes use of the on-resistance (r ds(on) ) of the low-side mosfet (q2 in the typical applications circuit ). when calculating the current limit, use the worst- case maximum value for r ds(on) from the mosfet data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% addi- tional resistance for each 1c of temperature rise. the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i lim(val) equals the minimum valley current-limit threshold voltage divided by the on-resistance of q2 (r ds(on)q2 ). for the 50mv default setting, connect ilim to av dd . in adjustable mode, the valley current-limit threshold is precisely 1/10th* the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd with ilim connected to the center tap. the external 250mv to 2v adjustment range corresponds to a 25mv to 200mv valley current-limit threshold. when adjusting the current limit, use 1% tolerance resistors and ii i lir lim val load max load max () ( ) () > ? ? ? ? ? ? - 2 pcvf rsnub snub in sw = 2 l fc par r par = () 1 2 2 pqvf r rr hsdr g gs sw gate gate dh = + . () i v rr gate on dh gate = + 25 pvif qq i hssw in load sw gs gd gate = + integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 22 ______________________________________________________________________________________ * in the negative direction, the adjustable current limit is typically -1/8th the voltage seen at ilim.
a divider current of approximately 10? to prevent signifi- cant inaccuracy in the valley current-limit tolerance. foldback current limit alternately, foldback current limit can be implemented if the uvp latch option is not available. foldback cur- rent limit reduces the power dissipation of external components so they can withstand indefinite overload and short circuit, with automatic recovery after the over- load or short circuit is removed. to implement foldback current limit, connect a resistor from v out to ilim (r6 in figure 7 and the typical applications circuit ), in addition to the resistor-divider network (r4 and r5) used for setting the adjustable current limit as shown in figure 7. the following is a procedure for calculating the value of r4, r5, and r6: 1) calculate the voltage, v ilim(nom) , required at ilim when the output voltage is at nominal: 2) pick a percentage of foldback, pfb, from 15% to 40%. 3) calculate the voltage, v ilim(0v) , when the output is shorted (0v): 4) the value for r4 can be calculated as: 5) the parallel combination of r5 and r6, denoted r56, is calculated as: 6) then r6 can be calculated as: 7) then r5 is calculated as: boost-supply diode and capacitor selection (buck) a low-current schottky diode, such as the cmdsh-3 from central semiconductor, works well for most appli- cations. do not use large-power diodes, because high- er junction capacitance can charge up the voltage at bst to the lx voltage and this exceeds the absolute maximum rating of 6v. the boost capacitor should be 0.1? to 4.7?, depending on the input and output volt- ages, external components, and pc board layout. the boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low- side mosfet conduction time, which happens at maxi- mum operating duty cycle (this occurs at minimum input voltage). in addition, ensure that the boost capac- itor does not discharge to below the minimum gate-to- source voltage required to keep the high-side mosfet r rr rr 5 656 656 = - r vrr vv v r vvr out out ilim nom ilim v ilim nom ilim v 6 6 56 0 0 = () () ? () () ? ? ? ? ? ? ? ? ? ? () () () () 4 5 -- 4- r v a r 56 2 10 = ? ? ? ? ? ? - 4 r vv a ilim v 4 2 10 0 = () - vpv ilim v fb ilim nom () ( ) 0 = vi lir r ilim nom load max ds on q () () () = ? ? ? ? ? ? 10 1 2 2 - max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 23 figure 7. foldback current limit max8550/ max8551 ref ilim gnd c ref r4 r6 r5 v out
max8550/max8551 fully enhanced for lowest on-resistance. this minimum gate-to-source voltage (v gs(min) ) is determined by: where v dd is 5v, q g is the total gate charge of the high-side mosfet, and c boost is the boost-capacitor value where c boost is c7 in the typical applications circuit (figure 8). transient response (buck) the inductor ripple current also affects transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. vvx q c gs min dd g boost () = integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 24 ______________________________________________________________________________________ figure 8. typical applications circuit max8550 ref ilim gnd pgnd1 dl vttr v dd fb dh lx bst v in av dd vtti vtt pok v in (4.5v to 28v) 2.5v / 12a vtt 1.25v / 1.5a 5v bias supply pok1 vttr 1.25v / 10ma pgnd2 refin vtts out stby pok2 ss ton ovp/uvp q1 irf7821 n-channel 30v, 9mw l1 toko fda1254-1r0m 1.0 h, 21a, 1.6m ? d1 cmosh-3 c11, c12 (150mf, 4v, 25mw, low-esr pos capacitor (d2e) sanyo 4tpe150m q2 irf7832 n-channel 30v,5mw c2 10 f c4 60 f c6 1 f r3 100k ? r4 187k ? r6 41.2k ? r5 20k ? r2 100k ? c9 3.9nf c10 0.22 f on off c11 150 f c12 150 f c13 1 f c7 0.22 f c5 4.7 f r1 10 ? c3 1 f c1 0.01 f c14 470 f (optional) skip shdna shdnb c8 2 x 10 f
the output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics ) and k is from table 1. the overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: applications information dropout performance (buck) the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable minimum off-time one-shot. for best dropout perfor- mance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propa- gation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (see table 1). also, keep in mind that transient-response perfor- mance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down indicates the controller? ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases, unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths ( see the on- time one-shot (ton) section), t off(min) is from the electrical characteristics , and k is taken from table 1. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then the operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. a dropout design example follows: v out = 2.5v f sw = 600khz k = 1.7? t off(min) = 450ns v drop1 = v drop2 = 100mv h = 1.5 voltage positioning (buck) in applications where fast-load transients occur, the output voltage changes instantly by r esr c out ? i load . voltage positioning allows the use of fewer out- put capacitors for such applications, and maximizes the output-voltage ac and dc tolerance window in tight-tolerance applications. figure 9 shows the connection of out and fb in a volt- age-positioned circuit. in nonvoltage-positioned cir- cuits, the max8550/max8551 regulate at the output capacitor. in voltage-positioned circuits, the max8550/ max8551 regulate on the inductor side of the voltage- positioning resistor. v out is reduced to: vv ri out vps out no load pos load () (_ ) = - v vv vns s vv v in min () . . . . . . . = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += 25 01 1 1 5 450 17 01 01 43 - - v vv ht k vv in min out drop off min drop drop () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 21 1- - v il cv soar load max out out = () ? 2 2 v li vk v t cv vv k v t sag load max out in off min out out in out in off min = + ? ? ? ? ? ? () + ? ? ? ? ? ? ? ? () () () ? 2 2 - max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 25
max8550/max8551 pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. the lx and pgnd1 connections to the low-side mosfet for current sensing must be made using kelvin-sense connections. when trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst, lx, dh, and dl) away from sensitive analog areas (ref, fb, and ilim). input ceramic capacitors must be placed as close as possible to the high-side mosfet drain and the low-side mosfet source. position the mosfets so the impedance between the input capacitor termi- nals and the mosfets is as low as possible. special layout considerations for ldo section the capacitor (or capacitors) at vtt should be placed as close to vtt and pgnd2 (pins 12 and 11) as possi- ble to minimize the series resistance/inductance of the trace. the pgnd2 side of the capacitor must be short with a low-impedance path to the exposed pad under- neath the ic. the exposed pad must be star-connected to gnd (pin 24), pgnd1 (pin 23), and pgnd2 (pin 11). a narrower trace can be used to connect the output voltage on the vtt side of the capacitor back to vtts (pin 9). however, keep this trace well away from poten- tially noisy signals such as pgnd1 or pgnd2. this prevents noise from being injected into the error ampli- fier? input. for best performance, the vtti bypass capacitor must be placed as close to vtti (pin 13) as possible. refin (pin 14) should be separately routed with a clean trace and adequately bypassed to gnd. refer to the max8550 evaluation kit data sheet for pc board guidelines. integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 26 ______________________________________________________________________________________ figure 9. voltage-positioned output max8550/ max8551 v in r pos fb out pgnd1 dl dh bst in lx gnd voltage- positioned output v dd av dd +5v bias supply
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards ______________________________________________________________________________________ 27 chip information transistor count: 5100 process: bicmos max8550/ max8551 ref ilim gnd pgnd1 dl vttr v dd fb dh lx bst v in av dd vtti vtt pok v in (4.5v to 28v) 1.8v - 2.5v / 12a vtt 0.9v - 1.25v / 1.5a 5v bias supply pok1 vttr 0.9v - 1.25v / 10ma pgnd2 refin vtts out stby pok2 ss ton ovp/uvp q1 q2 l1 c2 c4 c6 r3 r4 r6 r5 r2 c9 c10 on off c11 c7 c5 r1 10 ? c3 1 f c1 0.01 f skip shdna shdnb c8 typical operating circuit
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards 28 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l detail b l l1 e xxxxx marking f 1 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale-
max8550/max8551 integrated ddr power-supply solutions for desktops, notebooks, and graphic cards maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 29 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 y 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 n 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 y 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. f 2 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only.

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